Two versions of the single-cycle processor implementation for MIPS are
given in Patterson and Hennessey.
The first, Figure 4.17, shows an implementation
that omits the jump (j) instruction.
The second, Figure 4.24, includes the jump
instruction.
In order to understand these figures it is necessary to understand four things.
There are two kinds of logic circuitry: combinational logic and state elements. State elements retain information for the duration of a CPU cycle. During the clock cycle combinational logic generates new values for the state elements. These values are not captured by the state elements until the end of a cycle.
The clock time, one of the three factors in the performance equation, is set to be greater than the combinational gate delays plus any setup time required for state elements. The setup time is usually small compared to the combinational gate delays.
The control signals are grouped according to the following instruction execution activities.
A read control signal is sent to memory. The contents of the program counter (PC) are used as an address. Instruction fetch is the same for all instructions.
Instruction fetch is automatic, requiring no control signals.
The PC gets a new value selected from the following.
j and
jal instructions)
jr and
jalr instructions)
The most general way of implementing PC update is to have a PC source multiplexer with one input for each possible next PC value in the above list.
PC update may be done in more than one step in a multicycle implementation or a pipelined implementation. Then the processor typically does a simple increment (PC ← PC + 4) automatically, then make later modifications for branches, jumps, and interrupts.
The following are the control signals given in Patterson and Hennessey.
Asserted for branch instructions, ANDed with the ALU zero output to select the branch target address as the next instruction address.
Asserted for jump instructions, used to select the jump target address as the next instruction address. This signal is not included in Figure 4.17 of Patterson and Hennessey. It is included in Figure 4.24.
In the general implementation described above, the multiplexer control is a multibit signal with a value for each of the possible PC source values.
Instruction decoding produces controls signals for the datapath and memory. The inputs to control circuitry are the opcode and function fields of the instruction. It generates the following kinds of control signals.
Instruction decode is the same for all instructions.
Instruction decode is automatic, requiring no control signals.
The ALU is designed to combine two source operands to produce a result. The source operand fetch activity fetches the two source operands. One source operand is always specified by the rs instruction field. The other is selected from the following.
sltui
instruction)
In Patterson and Hennessey, this signal selects the second ALU input
from either rt or the sign-extended immediate field of the
instruction.
To deal with the sltiu instruction the ALUSrc
multiplexer needs an additional input: the zero-extended immediate
field.
An added value is needed for the ALUSrc control signal to select
this input.
For most instructions the ALU performs the operation suggested by the instruction mnemonic, which is coded into either the opcode or the function instruction field. For loads and stores the ALU computes the address, adding the sign extended immediate field of the instruction to the contents of the register specified by the rs field of the instruction. For branches the ALU can do a subtraction in order to compare two source operands, using the result to determine whether or not to do further a further update of the PC.
Determines the operation performed by the ALU. It has three values: "add", "subtract", or "decoded from function field". This signal is sent to the ALU Control circuitry. If ALUOp specifies "add" or "subtract", the ALU Control circuitry sends appropriate control signals for an add or subtract operation to the ALU. If ALUOp specifies "decoded from function field" then the ALU Control circuitry uses the function field to determine the control signal sent to the ALU.
To support all of the immediate operand instructions this signal would need two additional values: "and" and "or". The values are not included in Patterson and Hennessey.
A read or write control signal is sent to memory. The result from the ALU is used as an address.
Asserted for load instructions, tells memory to do a read.
Asserted for store instructions, tells memory to do a write.
Some instructions, such as branches, jumps, and stores, do not write to a register. For the instructions that do write to a register, the destination register can be one of the following.
jal instruction)
The value to be written to the register can come from the following places.
jal and jalr
instructions)
Asserted if a result is written to a register.
In Patterson and Hennessey, this selects the destination register as
either rd (R-type instructions) or rt (I-type instructions).
For jal the destination register of the register write
is $ra ($31).
To deal with the jal and jalr instructions
the RegDst multiplexer needs an additional input to select $ra: the
constant 111112.
An added value is needed for the RegDst control signal to select
this input.
In Patterson and Hennessey, this signal selects the source value for
the register write as either the ALU result or memory.
To deal with the jal and jalr instructions
the MemtoReg multiplexer needs an additional input for saving the
return address: PC + 4.
An added value is needed for the MemtoReg control signal to select
this input.
If this is done the MemtoReg signal should be renamed to something
like RegSrc.